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HEF4521B
24-stage frequency divider and oscillator
Rev. 05 -- 5 November 2009 Product data sheet
1. General description
The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) will function as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when pins VSS1 and VDD1 are supplied via external resistors. Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH-to-LOW transition of the clock (A2). The outputs from each of the last seven stages (218 to 224) are available for additional flexibility. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (-40 C to +85 C) temperature range.
2. Features
I I I I I I Low power crystal oscillator operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range -40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications
I Industrial
4. Ordering information
Table 1. Ordering information All types operate from -40 C to +85 C. Type number HEF4521BP HEF4521BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
5. Functional diagram
5 VDD1 A2 4 Y2 2 MR 9 A1
6
CP STAGES 1 to 8 CD Q8
3
VSS1
CP STAGES 9 to 16 CD Q16
CP STAGES 17 to 24 CD
Q24 Q18 Q19 Q20 Q21 Q22 Q23 1 10 11 12 13 14 15
Y1 7
001aae708
Fig 1.
Functional diagram
VDD1 VDD
A2
to FFs
to logic
VSS1 Y2
VSS
001aae711
Fig 2.
Schematic diagram of clock input circuitry
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
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Product data sheet Rev. 05 -- 5 November 2009 3 of 17
HEF4521B_5
NXP Semiconductors
Y2 A2 VSS1 VDD1
MR Q FF 1 T CD Q FF 2 T CD Q FF 3 T CD Q FF 4 T CD Q FF 5 T CD Q FF 6 T CD Q FF 7 T CD Q FF 8 T CD
A1
Q FF 9 T CD
Q FF 10 T CD
Q FF 11 T CD
Q FF 12 T CD
Q FF 13 T CD
Q FF 14 T CD
Q FF 15 T CD
Q FF 16 T CD
Q FF 17 T CD
Q FF 18 T CD
Q FF 19 T CD
Q FF 20 T CD
Q FF 21 T CD
Q FF 22 T CD
Q FF 23 T CD
Q FF 24 T CD
24-stage frequency divider and oscillator
Q24
Q18
Q19
Q20
Q21
Q22
Q23
Y1
001aae710
Fig 3.
Logic diagram
HEF4521B
(c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
6. Pinning information
6.1 Pinning
HEF4521B
Q24 MR VSS1 Y2 VDD1 A2 Y1 VSS 1 2 3 4 5 6 7 8
001aae709
16 VDD 15 Q23 14 Q22 13 Q21 12 Q20 11 Q19 10 Q18 9 A1
Fig 4.
Pin configuration
6.2 Pin description
Table 2. Symbol MR VSS1 VDD1 Y1, Y2 VSS A1, A2 Q18 to Q24 VDD Pin description Pin 2 3 5 7, 4 8 9, 6 10, 11, 12, 13, 14, 15, 1 16 Description master reset input ground supply voltage 1 supply voltage 1 external oscillator connection ground supply voltage external oscillator connection output supply voltage
7. Count capacity
Table 3. Output Q18 Q19 Q20 Q21 Q22 Q23 Q24 Count capacity Count capacity 218 = 262144 219 = 524288 220 = 1048576 221 = 2097152 222 = 4194304 223 = 8388608 224 = 16777216
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
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NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
8. Functional Test
A test function has been included to reduce the test time required to test all 24 counter stages. This test function divides the counter into three 8-stage sections by connecting VSS1 to VDD and VDD1 to VSS. 255 counts are loaded into each of the 8-stage sections in parallel via A2 (connected to Y2). All flip-flops are now at a HIGH level. The counter is now returned to the normal 24-stage in series configuration by connecting VSS1 to VSS and VDD1 to VDD. Entering one more pulse into input A2 will cause the counter to ripple from an all HIGH state to an all LOW state.
Table 4. Inputs MR H L A2 L Functional test sequence Control terminals Y2 L VSS1 VDD VDD1 VSS VSS Outputs Q18 to Q24 L H counter is in three 8-stage sections in parallel mode; A2 and Y2 are interconnected (Y2 is now input); counter is reset by MR. 255 pulses are clocked into A2, Y2. The counter advances on the LOW to HIGH transition. VSS1 is connected to VSS. the input A2 is made HIGH. VDD1 is connected to VDD; Y2 is now made floating and becomes an output; the device is now in the 224 mode. counter ripples from an all HIGH state to an all LOW state. Remarks
see see VDD Remarks Remarks column column L H H L L L VSS VSS VSS VSS
L L L L
[1]
VSS VSS VDD VDD
H H H L
H = HIGH voltage level; L = LOW voltage level; = HIGH to LOW transition.
9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot P
[1] [2]
Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation power dissipation
Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V to any supply terminal
Min -0.5 -0.5 -65 -40
Max +18 10 VDD + 0.5 10 10 100 +150 +85 750 500 100
Unit V mA V mA mA mA C C mW mW mW
DIP16 package SO16 package per output
[1] [2]
-
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
5 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
10. Recommended operating conditions
Table 6. Symbol VDD VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 -40 Typ Max 15 VDD +85 3.75 0.5 0.08 Unit V V C s/V s/V s/V
11. Static characteristics
Table 7. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 A 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 A 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = -40 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.7 -0.52 -1.3 -3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.3 20 40 80 Tamb = 25 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.4 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.3 20 40 80 7.5 Tamb = 85 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 150 300 600 V V V V V V V V V V V V mA mA mA mA mA mA mA A A A A pF Unit
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
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NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
12. Dynamic characteristics
Table 8. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuits see Figure 6; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions A2 to Q18; see Figure 5 VDD 5V 10 V 15 V Qn to Qn + 1; see Figure 5 5V 10 V 15 V MR to Qn 5V 10 V 15 V A1 to Y1; see Figure 5 5V 10 V 15 V tPLH LOW to HIGH propagation delay A2 to Q18; see Figure 5 5V 10 V 15 V Qn to Qn + 1; see Figure 5 5V 10 V 15 V A1 to Y1; see Figure 5 5V 10 V 15 V tt transition time Qn; see Figure 5 5V 10 V 15 V tW pulse width A2 HIGH; minimum width; see Figure 5 MR HIGH; minimum width; see Figure 5 trec recovery time MR; see Figure 5 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V fmax maximum frequency A1; see Figure 5 5V 10 V 15 V
[1]
[1] [1] [1]
Extrapolation formula 923 ns + (0.55 ns/pF) CL 339 ns + (0.23 ns/pF) CL 212 ns + (0.16 ns/pF) CL 13 ns + (0.55 ns/pF) CL 4 ns + (0.23 ns/pF) CL 2 ns + (0.16 ns/pF) CL 93 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 63 ns + (0.55 ns/pF) CL 24 ns + (0.23 ns/pF) CL 17 ns + (0.16 ns/pF) CL 923 ns + (0.55 ns/pF) CL 339 ns + (0.23 ns/pF) CL 212 ns + (0.16 ns/pF) CL 13 ns + (0.55 ns/pF) CL 4 ns + (0.23 ns/pF) CL 2 ns + (0.16 ns/pF) CL 33 ns + (0.55 ns/pF) CL 19 ns + (0.23 ns/pF) CL 12 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL
Min 80 40 30 70 40 30 +20 +15 15 6 12 17
Typ 950 350 220 40 15 10 120 55 40 90 35 25 950 350 220 40 15 10 60 30 20 60 30 20 40 20 15 35 20 15 -10 -5 0 12 25 35
Max 1900 700 440 80 30 20 240 110 80 180 70 50 1900 700 440 80 30 20 120 60 40 120 60 40 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
7 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (W) PD = 1200 x fi + (fo x CL) x VDD2
2
where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, (CL x fo) = sum of the outputs.
PD = 5100 x fi + (fo x CL) x VDD2 PD = 13050 x fi + (fo x CL) x VDD
13. Waveforms
VI MR input 0V tW 1/fmax VI A2 input 0V trec tPHL VOH Qn output VOL 10 % tt tt 001aae712 90 % tW tPLH VM VM
a. Pulse widths, maximum frequency, recovery and transition times and A2 to Qn propagation delays
VI A1 input VM VOH Qn output VM
0V
tPLH
tPHL
VOL VOH
tPLH
tPHL
VOH Y1 output VM
Qn + 1 output
VM
VOL Y1 propagation delays
VOL Qn to Qn + 1 propagation delays
001aak015
b. A1 to Y1, MR to Qn and Qn to Qn + 1 propagation delays
Measurement points are given in Table 10. The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig 5.
Waveforms showing measurement of dynamic characteristics
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
8 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
001aaj781
VM
VI positive pulse 0V
VM
a. Input waveforms
VDD VI G
RT
VO DUT
CL
001aag182
b. Test circuit
Test data is given in Table 10. Definitions for test circuit: Device Under Test (DUT); CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Table 10.
Test circuit for switching times Measurement points and test data Input VI VM 0.5VI tr, tf 20 ns VDD Load CL 50 pF
Supply voltage 5 V to 15 V
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
9 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
14. Application information
VDD
Ro 1.8 M R(1)
VDD A1
VDD1 Y1 Y2 Q18
A2
HEF4521B
CS CT
MR VSS
Q24 VSS1
R(1)
001aae713
(1) Optional for low power operation.
Fig 7.
Crystal oscillator circuit
Table 11. Typical characteristics for crystal oscillator See Figure 7. Parameter Crystal characteristics Resonance frequency Crystal cut Equivalent resistance; RS External resistor/capacitor values Ro CT CS 47 82 20 750 82 20 k pF pF 500 S 1 50 N 6.2 kHz k 500 kHz circuit 50 kHz circuit Unit
HEF4521B_5
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Product data sheet
Rev. 05 -- 5 November 2009
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NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
RTC C
VDD
102 fosc (kHz)
(1)
001aae715
RS
VDD A1
VDD1 Y1 Y2 Q18 10
(2)
A2
HEF4521B
1 MR VSS Q24 VSS1 10-1
001aae714
1 10-1
10 1
102 RTC (k) 103 10 C (nF) 102
1 f --------------------------------- ; R S 2R TC , where: 2.3 x R TC x C
f is in Hz, R is in , and C is in F.
VDD = 10 V; The test circuit is shown in Figure 8. (1) RTC; C = 1 nF; RS 2 RTC. (2) C; RTC = 56 k; RS = 120 k.
V IL ( max ) R S + R TC < -------------------- , where: I LI
VIL(max) = maximum input voltage LOW; and ILI = input leakage current.
Fig 8.
RC oscillator circuit
Fig 9.
Oscillator frequency as a function of RTC and C
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
11 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
12.5 gfs (mA/V) 10
(1)
001aae658
7.5
Rbias 560 k
(2)
5
(3)
VDD
0.47 F
A2 input
Y2 output
100 F
2.5 A
io
Vi (f = 1 kHz)
VSS
001aae820
0 0 5 10 VDD (V) 15
gfs = dio/dvi with vo constant (see Figure 11).
(1) Average + 2 s. (2) Average. (3) Average - 2 s, where `s' is the observed standard deviation.
Fig 10. Test setup for measuring forward transconductance
Fig 11. Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 C
75 gain (VO/VI) 50 typ
001aae716
20 IDD (mA) 15
001aae717
typ 10
25 5
0 0 5 10 VDD (V) 15
0 0 5 10 VDD (V) 15
Fig 12. Voltage gain VO/VI as a function of supply voltage
Fig 13. Supply current as a function of supply voltage
330 k
A2
Y2
001aae718
Fig 14. Test setup for measuring the Figure 12 and Figure 13 graphs
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
12 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
15. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 15. Package outline SOT38-4 (DIP16)
HEF4521B_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
13 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 16. Package outline SOT109-1 (SO16)
HEF4521B_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
14 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
16. Revision history
Table 12. Revision history Release date 20091105 Data sheet status Product data sheet Change notice Supersedes HEF4521B_4 Document ID HEF4521B_5 Modifications:
* * *
Section 2 "Features" ESD values removed. Section 10 "Recommended operating conditions" t/V values updated. Abbreviations section removed. Product data sheet Product specification Product specification HEF4521B_CNV_3 HEF4521B_CNV_2 -
HEF4521B_4 HEF4521B_CNV_3 HEF4521B_CNV_2
20090421 19950101 19950101
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
15 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4521B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 5 November 2009
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NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
19. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Count capacity . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 November 2009 Document identifier: HEF4521B_5

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